1. Field of the Invention
The present invention relates generally to power converter circuits and, in particular, to switched capacitor array circuits used in DCxe2x80x94DC converters.
2. Description of Related Art
Switched capacitor circuitry is used in several power converter applications and is particularly advantageous where the use of inductors is to be avoided. In a typical application, switched capacitor circuitry is used to convert a D.C. input voltage to one or more D.C. output voltages which may differ in magnitude and polarity from the input voltage. In some instances the circuitry includes some form of voltage regulation for controlling the magnitude of the output voltage notwithstanding changes in magnitude of the input voltage and changes in the load driven by the circuitry.
FIGS. 1A, 1B, 1C and 1D depict various states of a conventional capacitor array of the type which can be used in an integrated circuit voltage regulator, such as the conventional DCxe2x80x94DC voltage converter shown in FIG. 3. The converter includes a capacitor array circuit 10 comprised of three discrete capacitors A, B and C and several transistor switches which switch the capacitors into various configurations, such as those shown in FIGS. 1A, 1B, 1C and 1D.
As is well known, the capacitor array is switched between two states or phases so that the capacitors will be charged on one of the phases by a power source and so that the charge is transferred to a load in another of the phases. In some configurations, the power source operates to charge the array and the charge is transferred to the load in one or both of the two phases.
FIG. 1A is referred to as the common phase configuration of the capacitor array comprising capacitors A, B, C and the associated transistor switches (not depicted). FIGS. 1B, 1C and 1D are referred to as first, second and third gain phase configurations of the capacitor array. In operation, switch control circuitry 12 (FIG. 3) cause the array 10 to periodically switch between the common phase configuration (FIG. 1A) and one of the three gain phase configurations (FIGS. 1B, 1C and 1D). Thus, charge is periodically transferred from a power source (Vin) to a load connected to output Vsc.
The ratio Gsc of the output voltage Vsc of the capacitor array to the input voltage Vin is the gain state value of the array and is expressed as follows:
Gsc=Vsc/Vinxe2x80x83xe2x80x83(1) 
Gsc is based upon the output voltage Vsc when no load is connected to the array output other than a holding capacitor H. When a load is connected, voltage Vsc is reduced to the output voltage Vout, with the difference between Vout and Vsc being a function of, among other things, the net current delivered to the load.
Assuming that the gain phase configuration of the capacitor array is FIG. 1B, the value of Gsc can be determined by inspection. During the common phase configuration (FIG. 1A) the voltages across the three capacitors, VA, VB and VC are all equal to Vsc as follows:
VA=VB=VC=Vscxe2x80x83xe2x80x83(2) 
Note that the xe2x80x9c+xe2x80x9d sign on the capacitors identifies the capacitor terminal and not necessarily the polarity of the voltage across the capacitor. The input voltage Vin is, by inspection, as follows:
Vinxe2x88x92Vsc+(VA+VB+VC)xe2x80x83xe2x80x83(3) 
By combining equations (2) and (3), Vin=4Vsc so that Gsc is as follows:
Gsc=Vsc/Vin=xc2xcxe2x80x83xe2x80x83(4) 
Assuming that the FIG. 1C gain phase configuration is used, the input voltage Vin is, by inspection, as follows:
Vin=Vsc+(VA+VB)xe2x80x83xe2x80x83(5) 
By combining equations (2) and (5), Vin=3Vsc so that Gsc is as follows:
Gsc=Vsc/Vin=⅓xe2x80x83xe2x80x83(6) 
A similar analysis will confirm that the third gain phase configuration shown in FIG. 1D will produce a gain Gsc=xc2xd. Thus, all of the gains for the FIGS. 1A-1D array produce an output Vsc which is smaller than the input Vin.
Referring to FIG. 3, the converter utilizes a switched capacitor array 10, such as the array of FIGS. 1A-1D. The switch control circuitry 12 operates to control the state of the various transistor switches that are present in array 10 so that the array can assume any one of the configurations depicted in FIGS. 1A-1D. Gain setting circuitry 14 operates to control the switch control circuitry 12 so that the array will switch between the common phase configuration of FIG. 1A and a selected one of the gain phase configurations 1B-1D so as to provide three gain state values, with Gsc=xc2xd, ⅓ and xc2xc.
A clock circuit 20 provides a clock signal used by the switch control circuitry 12 to switch the transistor switches in array 10 with non-overlapping clock signals. One phase of the clock signal operates to turn off selected ones of the transistor switches and the second phase operates to turn on selected ones of the switches. The frequency F at which the switched capacitor array 10 switches between the common and the gain phase configurations will determine the effective output impedance Zout of the array as follows:
Zout xe2x88x9d1/(FC)xe2x80x83xe2x80x83(7) 
where C is the capacitance of the capacitors A, B and C. Thus, the output voltage Vout can be controlled by varying the value of the switching frequency F which will vary the voltage drop across Zout.
Regulation can be maintained only if a minimum gain state is maintained as will be explained.
Array 10 is capable of assuming different gain state values Gsc to increase the efficiency of the converter. The efficiency Eff of the converter can be generally expressed as follows:
Eff=Vout/(Gsc*Vin)xe2x80x83xe2x80x83(8) 
Thus, it can be seen that efficiency can be increased by using the smallest gain state value Gsc available, provided a minimum gain requirement is met. The gain state value Gsc must be at least large enough to ensure that the product of Gsc and Vin is larger than the desired output voltage. If this minimum gain requirement is not met, regulation of a voltage converter using the array cannot be carried out, as will be explained below in connection with equation (9).
The gain setting circuitry 14 of the FIG. 3 converter causes array 10 to change from one gain state value Gsc to another. The switch driver circuitry permits changes in gain state value to be made only when the array is in the common phase configuration. Thus, for example, when Gsc changes from ⅓ to xc2xd, the switch over occurs when the array is in the common phase configuration of FIG. 1A rather than going directly from the gain phase configuration of FIG. 1C (Gsc=⅓) to the gain phase configuration of FIG. 1D (Gsc=xc2xd).
Referring back to FIG. 3, a voltage reference circuit 26 produces reference voltage Vod indicative of the desired regulated output voltage Vout of the converter circuit. This value Vod is compared by a comparator circuit 24 with the actual output voltage Vout. The comparator output, sometimes referred to as signal Skip, has an average value inversely proportional to the load current provided by the converter circuit. Signal Skip is used to clock an up/down counter 16 which controls the gain setting circuitry 14. The up/down counter 16 has three output states that set the gain of the switched capacitor array 10 to one of the 3 gain state values (Gsc=xc2xd, ⅓ or xc2xc).
The output of the comparator circuit 24 is also used to control the state of logic circuitry represented by AND gate 18. As will be explained, gate 18 operates to either transfer or momentarily block the non-overlapping clock signals to the switch control circuitry 12 thereby controlling the amplitude of Vout by varying the value of Zout in accordance with equation (7). The switched capacitor array 10 must be in a gain state value Gsc which will be sufficiently large to permit voltage regulation. This is referred to as the minimum gain state value. An analog-to-digital converter (ADC) circuit 28 monitors the input Vin and output Vout and controls the gain setting circuitry 14 so that the switched capacitor array 10 will be at the minimum gain state value Gsc according to equation (9) below, with Gconv being the overall gain of the converter with regulation.
Gscxe2x89xa7Vout/Vin=Gconvxe2x80x83xe2x80x83(9) 
Thus, if the input voltage Vin was nominally +8 volts and the output voltage Vout is +2.4 volts, Gconv is 0.3 (2.4/8). Thus, ADC circuit 28 will prevent the gain setting circuitry 14 from providing a gain state value Gsc less than 0.3 under these circumstances since any lower value of Gsc will prevent the converter from regulating properly, even for small load currents.
Since the switched capacitor array provides only three discrete values of Gsc, the gain setting circuitry will set the minimum gain Gsc to ⅓ (0.33). Note also that if Gsc were exactly equal to Gconv, the converter would have essentially no output current capability so that it is likely that a higher gain state would be selected as will be explained.
The converter of FIG. 3 contains two control loops including a first loop which includes gate 18 and a second loop which includes gain setting circuitry 14. Assuming that the switched capacitor array 10 has sufficient gain Gsc in accordance with equation (9), changes in output voltage Vout will generally be attributable to changes in the load current or input Vin. As previously noted, the output of the comparator circuit 24, signal Skip, has an average value which is inversely proportional to the load current. If the load current should increase, output Vout will drop below Vod in which case the Skip output of comparator circuit 24 will go low thereby enabling gate 18 by way of inverter 22. Thus, the capacitor array 10 will be clocked, a process sometimes referred to as pumping, thereby increasing the output Vout.
If the actual output Vout exceeds the desired output Vod due to a drop in load current, the high Skip output of comparator circuit 24 will cause inverter 22 to disable gate 18 thereby inhibiting further pumping of the array 10. This will cause the output voltage Vout to drop (assuming there is some minimum load or leakage current). Once the output has dropped sufficiently, comparator circuit 24 will enable gate 18 so that pumping can resume. Thus, the first loop carries out a form of pulse frequency modulation (PFM) to control the output Vout in the presence of a change in load current for a particular gain state value Gsc for a given value of Vin. As will be explained below, the gain state value Gsc is set by the second loop.
ADC circuit 28, among other things, operates to assure that the array 10 provides the minimum gain Gsc necessary for regulation in accordance with equation (9). The second loop allows the gain Gsc to increase above the minimum gain based upon the load requirements. As previously noted, signal Skip has an average value inversely proportional to the load current. Thus, the second loop utilizes signal Skip to determine gain Gsc. If signal Skip is high for more than a first predetermined number of clock cycles, K=3 for example, the up/down counter 16 is decremented once thereby decreasing the gain state Gsc of array 10 by one step, provided the value of Gsc does not go below the minimum gain requirement. Alternatively, if signal Skip is low for more than a predetermined number of clock cycles, M=4 for example, the gain state value Gsc will be increased by one step.
Assuming in the previous example that the input Vin is +8 volts and the desired output Vod is +2.4 volts, the selected gain state Gsc is xc2xd and the actual output Vout is +2.55 volts. Under these conditions, it is possible to maintain Gsc at xc2xd and reduce the output Vout exclusively by way of the first loop by using pulse frequency modulation (PFM). However, in order to increase the efficiency, the up/down counter 16 is implemented so that it will be decremented one step after M=3 number of skipped pulses. This will cause the gain setting circuitry 14 to reduce the gain state value Gsc from xc2xd to ⅓. This will increase the converter efficiency as can be seen from equation (8).
The switched capacitor array of FIGS. 1A-1D provides gains Gsc that are less than one. Such arrays are limited to buck converters where the input voltage exceeds the desired output voltage. Boost converters produce an output voltage greater than the input voltage and thus require switched capacitor array providing gain state values Gsc greater than one.
FIGS. 2A-2G show a further prior art switched capacitor array which is capable of supporting both buck and boost converters. FIG. 2A is the common phase configuration where capacitors A, B and C are connected in parallel between input Vin and output Vsc. Thus, the FIG. 2A common phase configuration differs from that of FIG. 1A. FIGS. 2B through 2D are the gain phase configurations which provide gains Gsc of xc2xe, ⅔ and xc2xd, respectively. By way of example, it can be seen from FIG. 2A that the voltages across capacitors A, B, and C are the same and the input voltage Vin is as follows:
xe2x80x83Vsc=Vin+VA (or +VB or +VC)xe2x80x83xe2x80x83(10)
By inspection of FIG. 2B, it can be seen that the output voltage Vsc can also be expressed as follows:
Vsc=xe2x88x92(VA+VB+VC)=xe2x88x923VAxe2x80x83xe2x80x83(11) 
Combining equations (10) and (11), Vsc is as follows:
Vsc=Vinxe2x88x92Vsc/3xe2x80x83xe2x80x83(12) 
Thus, the gain state value Gsc for FIG. 2B is:
Gsc=Vsc/Vin=xc2xe (13) 
FIGS. 2E, 2F and 2G are the boost configurations. One or more of the capacitors A, B and C is connected in series between the input Vin and ground rather than between the output Vout and ground for the buck configurations previously described. Note also that the polarity of the capacitors is reversed. Referring to FIG. 2E in particular, it can be seen by inspection that the input voltage Vin is as follows:
Vin=VA+VB+VC=3VAxe2x80x83xe2x80x83(14) 
Combining equations (10) and (14) produces the following:
Vsc=Vin+Vin/3xe2x80x83xe2x80x83(15) 
Thus, from equation (15), it can be seen that FIG. 2E produces a Gsc=Vsc/Vin={fraction (4/3)}. A similar analysis shows that FIGS. 2F and 2G provide Gsc={fraction (3/2)} and 2, respectively.
The switched capacitor array of FIGS. 2A-2G can be used as array 10 of the FIG. 3 so that the converter has both buck and boost capabilities. Thus, for example, the converter would be capable of providing and output Vsc of +2.4 volts over a wide range of input voltages Vin, including voltages greater than +2.4 volts and less than +2.4 volts.
It can be seen from equation (8) that in order to increase efficiency, the value of Gsc should be not be any greater than necessary to provide the necessary load current at the desired output voltage. As previously described in connection with the FIG. 3 converter, should the value of Gsc be greater than necessary, this condition will be identified by signal Skip produced at the output of gate 18 being high for more than a predetermined number K clock cycles. However, since there are a limited number of discrete gain state values Gsc available, there will always be an inherent degree of inefficiency. The array of FIGS. 2A-2G produce six different gain values over a wide range, but efficiency can be increased by additional gain values or gain values that are more closely spaced over a smaller range.
As previously noted, it is highly preferred to have a common phase configuration, such a the phase configuration represented by FIG. 2A, associated with a group of gain phase configurations, such as the six gain phase configurations associated with FIGS. 2B-2G. It is not feasible to utilize gain phase configurations, such as shown in FIGS. 1B-1D, with the common phase configuration represented by FIG. 2A. Assume, for example, that an array 10 is configured to be switched between the configurations of FIGS. 1A/1D to provide a Gsc of xc2xd and then switched between the configurations of FIGS. 2A/2C to provide a Gsc of ⅔. The voltage across capacitor A will be xe2x88x92Vsc/2 per FIGS. 2A/2C and will be +Vsc per FIGS. 1A/1D. Since these voltages are not the same, the output of the array will assume some voltage which is inconsistant with Gsc=xc2xd and Gsc=⅔ and will, at minimum, reduce efficiency and will, at worst case, prevent regulation from taking place.
There is a need for switched capacitor array capable of providing an increased number of gain phase configurations which have a common phase configuration. The present invention addresses this shortcoming of the prior art and is capable of providing switched capacitor arrays having a common phase configuration and a large number of compatible gain phase configurations. This and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.
A switched capacitor array circuit coupled between an input node and an output node and capable of providing multiple gain state values is disclosed. The array circuit includes an L bank of capacitor positions disposed intermediate the input node and a third node, typically circuit common, with the L bank capacitor bank positions consisting of series capacitor positions and parallel capacitor positions. An M bank of capacitor positions is included which is disposed intermediate the input node and the output node, with the M bank capacitor bank positions also consisting of series capacitor positions and parallel capacitor positions. Further, an N bank of capacitor positions is provided which is disposed intermediate the output node and the third node, with the N bank capacitor bank positions consisting of series capacitor positions and parallel capacitor positions.
One embodiment of the invention includes first, second and third capacitors together with switching circuitry coupled to the capacitors and to the input node, the output node and the third node. Also included is control circuitry coupled to the switching circuitry and configured to switch the switched capacitor array circuit between a common phase configuration and a gain phase configuration so as to provide a gain state value Gsc. In the gain phase configuration, the first and second capacitors are disposed in one of the L, M and N bank of capacitor positions. The third capacitor is disposed in a different one of the L, M and N bank of capacitor positions in the common phase configuration. When switching from the common phase configuration to the gain phase configuration, at least one of the first, second and third capacitors is moved from a common phase configuration position to a gain position different than the common phase configuration position. The capacitors that are disposed in the series capacitor position in the common phase configuration are disposed in the parallel capacitor position in the gain phase configuration and the capacitors that are disposed in the parallel capacitor position in the common phase configuration are disposed in the series capacitor position in the gain phase configuration.